1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register capable of reducing the voltage stress effect.
2. Description of the Related Art
Liquid crystal displays, on account of their high resolution requirement, are widely applied to various electronic devices, such as mobile phones, personal digital assistants, digital cameras, computer displays, and notebook computer displays.
FIG. 1 shows a functional block diagram of a conventional liquid crystal display 10. The liquid crystal display 10 includes a liquid crystal panel 12, a gate driver 14, and a source driver 16. The liquid crystal panel 12 includes a plurality of pixels, each pixel having three pixel units 20 indicating three primary colors, red, green, and blue. For example, the liquid crystal display 12 with 1024 by 768 pixels contains 1024×768×3 pixel units 20. The gate driver 14 periodically outputs a scanning signal to turn on each transistor 22 of the pixel units 20 row by row, meanwhile, each pixel units 20 is charged to a corresponding voltage based on a data signal from the source driver 16, to show various gray levels. After a row of pixel units is finished to be charged, the gate driver 14 stops outputting the scanning signal to this row, and then outputs the scanning signal to turn on the transistors 22 of the pixel units of the next row. Sequentially, until all pixel units 20 of the liquid crystal panel 12 finish charging, and the gate driver 14 outputs the scanning signal to the first row again and repeats the above-mentioned mechanism.
As to the conventional liquid crystal display, the gate driver 14 functions as a shift register. In other words, the gate driver 16 outputs a scanning signal to the liquid crystal display 12 at a fixed interval. For instance, a liquid crystal display 12 with 1024×768 pixels and its operating frequency with 60 Hz is provided, the display interval of each frame is about 16.67 ms (i.e., 1/60 second), such that an interval between two scanning signals applied on two row adjacent lines is about 21.7 μs (i.e., 16.67 ms/768). The pixel units 20 are charged and discharged by data voltage from the source driver 16 to show corresponding gray levels in the time period of 21.7 μs accordingly.
Unfortunately, regarding the gate driver 14 manufactured with an amorphous silicon (a-Si) technology, the liquid crystal display 12 may display unevenly due to a voltage stress phenomenon which causes a discrepancy of threshold voltages of any two transistors. FIG. 2 is a block diagram of a shift register disclosed in U.S. Pat. No. 5,222,082. FIG. 3 is a circuit diagram of the shift register as shown in FIG. 2. FIG. 4 is a timing diagram of each node as shown in FIG. 3. The shift register 30 includes a plurality of shift register units 31 electrically coupled in cascade. Each shift register unit 31 is used for delaying an input signal INPUT from an input end 32 and outputting an output signal OUTPUT1 to a output end 33, based on clock signals C1, C2, and C3 of the clock generator 38. Then the next register unit 31 delays the output signal OUTPUT1 of the previous register unit 3, and thus outputs an output signal OUTPUT2. Referring to FIG. 4, the output signal OUTPUT of each register unit 31 is a delay of the input signal INPUT. However, as range A shown in FIG. 4, voltage applied at gates (i.e. node P2) of transistors 17 and 19 of each register unit 31 may keep a high voltage level for a long while until next scanning period for the next frame. In this way, the gate voltage Vg applied to the transistors 17 and 19 results in a voltage shift.
FIG. 5 is a chart illustrating a relationship between the gate voltage and the drain current corresponding to various voltage stresses. FIG. 5 is cited based on the content of Japan. Journal of Applied Physics Vol. 37 (1998) pp. 4704-4710. When the transistor is under a positive voltage stress, the longer the stress time is, the greater the shift range of threshold voltage Vth of the transistor is. However, the stress time of the positive voltage stress may degrade operation efficiency and reduce the life of the transistor, even shorten the life of the whole shift register.
In order to reduce the damage of the transistor caused by the voltage stress phenomenon that the high voltage level is applied at the gate of the transistor for a long while, a resolution is to shorten a time period over which the high voltage level is applied at the gate of the transistor.
Referring to FIGS. 6 and 7, FIG. 6 is a block diagram of a shift register disclosed in U.S. Pat. No. 5,517,542, and FIG. 7 is a block diagram of a shirt register disclosed in U.S. Pat. No. 6,845,140. In FIG. 6, the delay output of the Nth stage shift register unit 42 is controlled by the output OUTn+2 of the (N+2)th stage shift register unit 42. In FIG. 7, the delay output of the Nth stage shift register unit SRN is controlled by the output GOUTN+1 of the (N+1)th stage shift register unit SRN+1. In other words, a transition of the gate voltage of the current transistor from the high voltage level to the low voltage level is determined by the output signal of the next stage or the next two stage shift register unit of such two shift registers, so that the voltage applied on the gate of the transistor does not keep the high voltage level for a long time, thereby reducing voltage stress phenomenon for the transistor. Because such two shift register units utilize the output signal of next stage or next two stage shift register units as a control signal to adjust the transition of the gate voltage of the transistor of the current shift register unit, the signal interference inevitably occurs.